Samsung and IBM Could Break the Nanosheet Threshold in Chips With 'Vertically Stacked Transistors'

This design can either double the performance of chips or reduce power use by 85%.

In May of 2021, we brought you a breakthrough in semiconductor materials that saw the creation of a chip that could push back the "end" of Moore's Law and further widen the capability gap between China and U.S.-adjacent efforts in the field of 1-nanometer chips.

The breakthrough was accomplished in a joint effort, involving the Massachusetts Institute of Technology (MIT), National Taiwan University (NTU), and the Taiwan Semiconductor Manufacturing Co (TSMC), which is the world's largest contract manufacturer of advanced chips. At the core of the breakthrough was a process that employs semi-metal bismuth to allow for the manufacture of semiconductors below the 1-nanometer (nm) level.

Now, IBM and Samsung claim they have also made a breakthrough in semiconductor design, revealing a new concept for stacking transistors vertically on a chip, according to a press release acquired by IE. It's called Vertical Transport Field Effect Transistors (VTFET) and it sees transistors lie perpendicular to one another while current flows vertically.

This is a drastic change from today's models where transistors lie flat on the surface of the silicon, and then electric current flows from side to side. By doing this, IBM and Samsung hope to extend Moore’s Law beyond the nanosheet threshold and waste less energy.

What will that look like in terms of processors? Well, IBM and Samsung state that these features will double the performance or use 85 percent less power than chips designed with FinFET transistors. But these two firms are not the only ones testing this type of technology.

Intel is also experimenting with chips stacked above each other, as reported by Reuters. "By stacking the devices directly on top of each other, we're clearly saving area," Paul Fischer, director and senior principal engineer of Intel's Components Research Group told Reuters in an interview. "We're reducing interconnect lengths and really saving energy, making this not only more cost efficient, but also better performing."

All these advances are great for our cell phones who could one day go weeks without charging and for energy-intensive activities such as crypto mining. But then, we might also find ourselves in a Jevon's paradox, which occurs when technological progress increases the efficiency with which a resource is used, but the rate of consumption of that resource also rises due to increasing demand. Isn't that what's going on with cryptocurrencies in a way?

Update: A previous version of this article claimed that these features would yield double the performance and use 85 percent less power compared to chips designed with FinFET transistors. In reality, the new design can do either of these at a single moment. It can either double the performance or use 85 percent less power. And mentions of "sub-1nm" were changed with "nanosheet" to better reflect the research.

Source: https://interestingengineering.com/samsung-ibm-could-break-1nm-threshold-in-chips-with-stacked-transistors